1. Field
Various embodiments of the present invention relate to an error controlling system, a processor and an error injection method.
2. Description of the Related Art
An ordinary information processing apparatus such as a server is provided with a mechanism to be ready for an occurrence of an error and to solve the error in some cases. An enterprise server is required as an information processing apparatus to be reliable enough to continue operation without outputting an incorrect result even in case of an error occurrence, and an ordinary processor for server-use such as a CPU (Central Processing Unit) to be integrated in such an enterprise server is provided with mechanisms for detecting an error and for recovering from the error.
An error that occurs in an information processing apparatus may be, e.g., a permanent error of a semiconductor component caused by poor hardware manufacturing or aging degradation, or an intermittent soft error occurrence caused in a semiconductor component by cosmic rays or radial rays.
An information processing apparatus provided with a mechanism for detecting and recovering from an error, so-called a RAS (Reliability, Availability and Serviceability) mechanism, is generally required to examine an operation of the RAS mechanism. It is difficult to check whether the RAS mechanism correctly works after an error actually occurs. Thus, a circuit in which a pseudo error is embedded for checking an operation of the RAS mechanism is typical.
An error injection circuit has successively increased pseudo error generating patterns in accordance with error modes which have ordinarily occurred, where various pseudo error generating mechanisms have been devised. To put it specifically, an art for integrating a plurality of errors between an instruction to start to generate a pseudo error and an instruction to finish generating the pseudo error or for a regular period of time since the instruction to start to generate the pseudo error is typical. Further, an art for generating pseudo errors a specified number of times is typical as well.
As an integrated circuit has acquired large-scale integration and high-speed performance, a problem has occurred in an arrangement of the RAS mechanism. One reason is, although a circuit to be a target for pseudo error generation is required to be reachable from the pseudo error generating mechanism within one cycle of a operating frequency of the integrated circuit, a propagation delay of a signal of the pseudo error generation turns not to be disregarded as the integrated circuit has acquired large-scale integration and high-speed performance.
Arts related to the error controlling are discussed in Japanese Laid-open Patent Publications Nos. 56-021253, 64-082140, 01-261732, 58-039351, 59-087560 and 04-369046.
Embodiments described herein have been developed in view of the above and other problems of the typical system including for the purpose of providing an error controlling system, a processor and an error injection method for which the propagation delay of the signal of the pseudo error generation is considered.
According to an error controlling system, a processor and an error injection method disclosed herein, among others, an effect is obtained such that an error controlling system, a processor and an error injection method for which a propagation delay of a signal of the pseudo error generation is considered can be provided.